View TDA8030_39054.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
DATA SHEET
TDA8030; TDA8031 USB smart card reader (OTP or ROM)
Product specification 2003 Jul 04
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.4 8.4.1 FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING TDA8030 TDA8031 FUNCTIONAL DESCRIPTION ISO7816 UART AND ASSOCIATED LOGIC Interface control Control registers General registers ISO UART REGISTERS CARDS REGISTERS Registers summary SUPPLY Power switch control 3.3 V regulator DC-to-DC converter Supply supervisor ISO7816 SECURITY Introduction Protections and limitations Activation sequence Deactivation sequence MICROCONTROLLER Low power modes 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.5.6 8.5.7 8.5.8 8.5.9 9 10 11 12 13 14 14.1 14.2 14.3 14.4 14.5 15 16 17
TDA8030; TDA8031
USB INTERFACE End-points Phase-locked loop Bit clock recovery Interface signals with the microcontroller Block diagram USB registers Instruction set Analog interface Suspend mode LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS
2003 Jul 04
2
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
1 FEATURES
TDA8030; TDA8031
* 83C51 core with 16 kbytes EPROM (ROM); 256 bytes RAM; 512 bytes AUXRAM; Timer 0,1, 2 and enhanced UART * Full speed USB interface device which complies with USB 1.1 specification; accessible with MOVX instructions * Control input and output; 1 generic input and output and 2 generic input end-points * Compatible with bus powered and suspend mode supply current requirements * Specific ISO7816 UART; accessible with MOVX instructions for automatic convention processing; variable baud rate through frequency or division ratio programming; error management at character level for T = 0 protocol; extra guard time register * VCC generation (5 or 3 V maximum current 55 mA or 1.8 V maximum current 35 mA) with controlled rise and fall times; current limitation and overload detection at 100 mA * Cards clock generation with three times synchronous frequency doubling (12, 6, 3 and 1.5 MHz) * Cards clock STOP HIGH or LOW or 1.25 MHz (from an integrated oscillator) for cards power reduction mode * Automatic activation and deactivation sequences through an independent sequencer * Supports the asynchronous protocols T = 0 and T = 1 in accordance with ISO7816 and EMV * Versatile 24-bit time-out counter for Answer To Reset (ATR) and waiting times processing * Supports synchronous cards * Specific Elementary Time Unit (ETU) counter for Block Guard Time (BGT) 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8030HL TDA8031HL LQFP64 DESCRIPTION plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm VERSION SOT314-2 * Current limitations on cards contacts and emergency deactivation in case of over consumption or overheating * Special circuitry for killing spikes during power-on or power-off * Supply supervisor for power-on or power-off reset * High efficiency inductive DC-to-DC converter for VCC generation * Soft switch on for avoiding current inrush at plug in * Enhanced ESD protections on cards contacts (6 kV minimum) * Software library for easy integration within the application. 2 APPLICATIONS
* Smart card readers for PC's or Set Top Boxes. 3 GENERAL DESCRIPTION
The TDA8030; TDA8031 is a bus powered full-speed USB device. All analog and digital functions for an EMV compliant Smart Card Reader are built-in. The embedded 83C51 microcontroller has 16 kbytes EPROM (ROM for TDA8031), 256 bytes RAM and 512 bytes of AUXRAM.
2003 Jul 04
3
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
5 QUICK REFERENCE DATA PARAMETER bus supply voltage bus supply current suspend current card supply voltage VCC = 5 V; ICC = 40 mA; fclk = 6 MHz card inactive; microcontroller in Power-down mode including static load; 5 V card with dynamic loads on 200 nF including static loads; 3 V card with dynamic loads on 200 nF including static loads; 1.8 V card with dynamic loads on 200 nF ICC card supply current 5 V card 3 V card 1.8 V card Ilim Iod Tamb current limit on VCC overload detection on VCC ambient temperature CONDITIONS - - 4.75 4.60 2.85 2.75 1.64 1.62 - - - - - -25
TDA8030; TDA8031
SYMBOL VDDU IDDU Isus VCC
MIN. 4.2 - - - 5 - 3 -
TYP.
MAX. 5.5 100 500 5.25 5.40 3.15 3.25 1.96 1.98 -55 -55 -35 100 100 +85
UNIT V mA A V V V V V V mA mA mA mA mA C
1.8 - - - - - - -
2003 Jul 04
4
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
6 BLOCK DIAGRAM
TDA8030; TDA8031
handbook, full pagewidth
VDD 6.8 H
CDELAY 31 RESET 7 SUPPLY SUPERVISOR
LX 24 23 VUP STEP-UP CONVERTER 1 F 25 STGND
EA/VPP PSEN ALE/PROG
54 52 53 63, 64, 1 to 6 32 to 39 8xC51 MICROCONTROLLER 16 kbytes EPROM 256 bytes RAM TIMER 0, 1, 2 ENHANCED UART P32/INT0 44 to 51 62 to 55 12 42 CDEC 1 F 3.3 V LDO
TIME-OUT COUNTER
ISO7816 UART ANALOG DRIVERS AND SEQUENCER
P10 to P17 P30 to P37
CLOCK CIRCUITRY
20 21 18 19 13 17 15 16
P33/INT1
VCC RST CGND CLK I/O C4 C8 PRES
P20 to P27 P00 to P07 CPROG VDDD DGND VDDU UGND VDD 10 F D+ D- DELATT
TDA8030
ALE P36/WR P37/RD 512 bytes AUXRAM 22 POWER SWITCH CONTROL PLL XTAL OSCILLATOR TEST INTERFACE CONTROL
43 27 28 26
41 40
XTAL1 XTAL2
29 30 10 USB ATX USB INTERFACE INTERNAL OSCILLATOR
8 RFU
9 RFU
11 RFU
14
MGU881
RFU
Fig.1 Block diagram (TDA8030).
2003 Jul 04
5
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
handbook, full pagewidth
VDD 6.8 H
CDELAY 31 RESET 7 SUPPLY SUPERVISOR
LX 24 23 VUP STEP-UP CONVERTER 1 F 25 STGND
EA PSEN ALE
54 52 53 63, 64, 1 to 6 32 to 39 8xC51 MICROCONTROLLER 16 kbytes EPROM 256 bytes RAM TIMER 0, 1, 2 ENHANCED UART P32/INT0 44 to 51 62 to 55
TIME-OUT COUNTER
ISO7816 UART ANALOG DRIVERS AND SEQUENCER
P10 to P17 P30 to P37
CLOCK CIRCUITRY
20 21 18 19 13 17 15 16
P33/INT1
VCC RST CGND CLK I/O C4 C8 PRES
P20 to P27 P00 to P07 VDDD CDEC 1 F DGND
TDA8031
ALE 42 3.3 V LDO P36/WR P37/RD 512 bytes AUXRAM 22 POWER SWITCH CONTROL PLL XTAL OSCILLATOR TEST INTERFACE CONTROL
43
VDDU UGND VDD 10 F D+ D- DELATT
27 28 26
41 40
XTAL1 XTAL2
29 30 10 USB ATX USB INTERFACE INTERNAL OSCILLATOR
12
8, 11 2
9, 14
MGU882
2 RFU
SCANEN
RFU
Fig.2 Block diagram (TDA8031).
2003 Jul 04
6
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
7 7.1 PINNING TDA8030 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 DESCRIPTION 8xC51 general purpose I/O port (USB_MC_READY) 8xC51 general purpose I/O port (USB_CLK_EN_N) 8xC51 general purpose I/O port (USB_RESET_N)
TDA8030; TDA8031
SYMBOL P12 P13 P14 P15 P16 P17 RESET RFU RFU DELATT RFU CPROG I/O RFU C8 PRES C4 CGND CLK VCC RST TEST VUP LX STGND VDD VDDU UGND D+ D- CDELAY P30/RxD P31/TxD P32/INT0 P33/INT1
8xC51 general purpose I/O port (USB_SOFTCONNECT_EXT) 8xC51 general purpose I/O port (available for the application) 8xC51 general purpose I/O port (available for the application) reset input (active HIGH, integrated pull-down resistor to ground) test pin; leave open-circuit in the application test pin; leave open-circuit in the application delayed attachment reference signal output for external pull-up resistor on pin D+ (an internal 1.5 k pull-up resistor is already embedded on-chip) test pin; leave open-circuit in the application connect to GND within the application; for programming the EPROM connect to VDD as well as pin TEST (pin 22); also used for test purposes data input/output from the card (C7); 14 k integrated pull-up resistor connected to VCC test pin; leave open-circuit in the application auxiliary I/O for C8 contact; 14 k integrated pull-up resistor connected to VCC card presence detection input (active HIGH; no need for external pull-up) auxiliary I/O for C4 contact; 14 k integrated pull-up resistor connected to VCC cards ground (C5) Must be connected to GND clock output (C30) card supply output voltage (ISO C1 contact); must be decoupled with two 100 nF low ESR ceramic capacitors to CGND cards reset output (C2) test pin input output of the DC-to-DC converter (decouple with a 1 F capacitor to STGND) DC-to-DC converter inductor connection (a Schottky diode should be tied to VUP) DC-to-DC converter ground connection soft switched positive supply voltage (decouple with 10 F capacitor to GND) positive supply voltage for the bus (4.2 to 5.5 V) bus ground USB D+ data line USB D- data line connection for an external capacitor to ground determining the Power-on reset pulse width (typ 1 ms per 2 nF) 8xC51 general purpose I/O port/serial input port (available for the application) 8xC51 general purpose I/O port/serial output port (available for the application) 8xC51 general purpose I/O port/external interrupt 0 (used by the ISO UART)) 8xC51 general purpose I/O port/external interrupt 1 (used by the USB interface)
2003 Jul 04
7
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
SYMBOL P34 P35 P36/WR P37/RD XTAL2 XTAL1 VDDD DGND P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 PSEN
PIN 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
DESCRIPTION 8xC51 general purpose I/O port (USB_SUSPEND in TDA8030) 8xC51 general purpose I/O port (USB_WAKEUP_N in TDA8031) external data memory write strobe external data memory read strobe 12 MHz crystal output; leave open-circuit if an external clock is used external 12 MHz crystal connection or input for an external clock signal 3.3 V regulated digital supply voltage output (decouple with 1 F ceramic capacitor) Digital ground 8xC51 general purpose I/O port/address 8 (available for the application) 8xC51 general purpose I/O port/address 9 (available for the application) 8xC51 general purpose I/O port/address 10 (available for the application) 8xC51 general purpose I/O port/address 11 (available for the application) 8xC51 general purpose I/O port/address 12 (available for the application) 8xC51 general purpose I/O port/address 13 (USB_MP_C) 8xC51 general purpose I/O port/address 14 (USB_MP_SEL) 8xC51 general purpose I/O port/address 15 (ISO_UART_CS) Program Store Enable: read strobe to external program memory when executing code from the external program memory; PSEN is activated twice each machine cycle except when two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. Address Latch Enable/Program Pulse: output pulse for latching the low byte of the address during an access to external memory. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency and can be used for external timing or clocking. It should be noted that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during EPROM programming. ALE can be disabled by setting SFR Auxiliary0. With this bit set ALE will be active only during a MOVX instruction. External Access Enable/Programming Supply Voltage: EA must be externally held LOW to enable the device to fetch code from external program memory locations starting with 0000H. If EA is held HIGH the device executes from internal program memory unless the program counter contains an address greater than 3FFFH (16 kbytes boundary). This pin also receives the 12.75 V programming supply voltage (VPP) during EPROM programming. If security bit 1 is programmed EA will be internally latched on reset. 8xC51 general purpose I/O port/address/data 7 8xC51 general purpose I/O port/address/data 6 8xC51 general purpose I/O port/address/data 5 8xC51 general purpose I/O port/address/data 4 8xC51 general purpose I/O port/address/data 3 8xC51 general purpose I/O port/address/data 2 8xC51 general purpose I/O port/address/data 1 8xC51 general purpose I/O port/address/data 0 8xC51 general purpose I/O port (USB_INT_MASK) 8xC51 general purpose I/O port (USB_SOFTCONNECT_INT)
ALE/PROG
53
EA/VPP
54
P07/AD7 P06/AD6 P05/AD5 P04/AD4 P03/AD3 P02/AD2 P01/AD1 P00/AD0 P10 P11
55 56 57 58 59 60 61 62 63 64
2003 Jul 04
8
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
handbook, full pagewidth
53 ALE/PROG
62 P00/AD0
61 P01/AD1
60 P02/AD2
59 P03/AD3
58 P04/AD4
57 P05/AD5
56 P06/AD6
55 P07/AD7
51 P27/A15
50 P26/A14
P12 1 P13 2 P14 3 P15 4 P16 5 P17 6 RESET 7 RFU 8
49 P25/A13
54 EA/VPP
52 PSEN
64 P11
63 P10
48 P24/A12 47 P23/A11 46 P22/A10 45 P21/A9 44 P20/A8 43 DGND 42 VDDD 41 XTAL1
TDA8030
RFU 9 DELATT 10 RFU 11 CPROG 12 I/O 13 RFU 14 C8 15 PRES 16 VCC 20 RST 21 TEST 22 VUP 23 LX 24 STGND 25 VDD 26 VDDU 27 UGND 28 D + 29 D- 30 CDELAY 31 P30/RxD 32 C4 17 CGND 18 CLK 19 40 XTAL2 39 P37/RD 38 P36/WR 37 P35 36 P34 35 P33/INT1 34 P32/INT0 33 P31/TxD
MGU883
Fig.3 Pin configuration (top view).
2003 Jul 04
9
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
7.2 TDA8031 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 DESCRIPTION 8xC51 general purpose I/O port (USB_MC_READY) 8xC51 general purpose I/O port (USB_CLK_EN_N) 8xC51 general purpose I/O port (USB_RESET_N)
TDA8030; TDA8031
SYMBOL P12 P13 P14 P15 P16 P17 RESET RFU RFU DELATT RFU SCANEN I/O RFU C8 PRES C4 CGND CLK VCC RST TEST VUP LX STGND VDD VDDU UGND D+ D- CDELAY P30/RxD P31/TxD P32/INT0 P33/INT1 P34
8xC51 general purpose I/O port (USB_SOFTCONNECT_EXT) 8xC51 general purpose I/O port (available for the application) 8xC51 general purpose I/O port (available for the application) reset input (active HIGH, integrated pull-down resistor to ground) test pin; leave open-circuit in the application test pin; leave open-circuit in the application delayed attachment reference signal output for external pull-up resistor on pin D+ (an internal 1.5 k pull-up resistor is already embedded in the chip) test pin; leave open-circuit in the application connect to GND within the application; for programming the EPROM connect to VDD as well as pin TEST (pin 22); also used for test purposes data input/output from the card (C7); 14 k integrated pull-up resistor connected to VCC test pin; leave open-circuit in the application auxiliary I/O for C8 contact; 14 k integrated pull-up resistor connected to VCC card presence detection input (active HIGH; no need for external pull-up) auxiliary I/O for C4 contact; 14 k integrated pull-up resistor connected to VCC cards ground (C5) Must be connected to GND clock output (C30) card supply output voltage (ISO C1 contact); must be decoupled with two 100 nF low ESR ceramic capacitors to CGND cards reset output (C2) test pin input output of the DC-to-DC converter (decouple with a 1 F capacitor to STGND) DC-to-DC converter inductor connection (a Schottky diode should be tied to VUP) DC-to-DC converter ground connection soft switched positive supply voltage (decouple with 10 F capacitor to GND) positive supply voltage for the bus (4.2 to 5.5 V) bus ground USB D+ data line USB D- data line connection for an external capacitor to ground determining the Power-on reset pulse width (typ 1 ms per 2 nF) 8xC51 general purpose I/O port/serial input port (available for the application) 8xC51 general purpose I/O port/serial output port (available for the application) 8xC51 general purpose I/O port/external interrupt 0 (used by the ISO UART)) 8xC51 general purpose I/O port/external interrupt 1 (used by the USB interface) 8xC51 general purpose I/O port (USB_SUSPEND in TDA8030)
2003 Jul 04
10
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
SYMBOL P35 P36/WR P37/RD XTAL2 XTAL1 VDDD DGND P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 PSEN
PIN 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 external data memory write strobe external data memory read strobe
DESCRIPTION 8xC51 general purpose I/O port (USB_WAKEUP_N in TDA8030)
12 MHz crystal output; leave open-circuit if an external clock is used external 12 MHz crystal connection or input for an external clock signal 3.3 V regulated digital supply voltage output (decouple with 1 F ceramic capacitor) Digital ground 8xC51 general purpose I/O port/address 8 (available for the application) 8xC51 general purpose I/O port/address 9 (available for the application) 8xC51 general purpose I/O port/address 10 (available for the application) 8xC51 general purpose I/O port/address 11 (available for the application) 8xC51 general purpose I/O port/address 12 (available for the application) 8xC51 general purpose I/O port/address 13 (USB_MP_C) 8xC51 general purpose I/O port/address 14 (USB_MP_SEL) 8xC51 general purpose I/O port/address 15 (ISO_UART_CS) Program Store Enable: read strobe to external program memory when executing code from the external program memory; PSEN is activated twice each machine cycle except when two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. Address Latch Enable/Program Pulse: output pulse for latching the low byte of the address during an access to external memory. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency and can be used for external timing or clocking. It should be noted that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during EPROM programming. ALE can be disabled by setting SFR Auxiliary0. With this bit set ALE will be active only during a MOVX instruction. External Access Enable/Programming Supply Voltage: EA must be externally held LOW to enable the device to fetch code from external program memory locations starting with 0000H. If EA is held HIGH the device executes from internal program memory unless the program counter contains an address greater than 3FFFH (16 kbytes boundary). This pin also receives the 12.75 V programming supply voltage (VPP) during EPROM programming. If security bit 1 is programmed EA will be internally latched on reset. 8xC51 general purpose I/O port/address/data 7 8xC51 general purpose I/O port/address/data 6 8xC51 general purpose I/O port/address/data 5 8xC51 general purpose I/O port/address/data 4 8xC51 general purpose I/O port/address/data 3 8xC51 general purpose I/O port/address/data 2 8xC51 general purpose I/O port/address/data 1 8xC51 general purpose I/O port/address/data 0 8xC51 general purpose I/O port (USB_INT_MASK) 8xC51 general purpose I/O port (USB_SOFTCONNECT_INT)
ALE
53
EA
54
P07/AD7 P06/AD6 P05/AD5 P04/AD4 P03/AD3 P02/AD2 P01/AD1 P00/AD0 P10 P11
55 56 57 58 59 60 61 62 63 64
2003 Jul 04
11
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
62 P00/AD0
61 P01/AD1
60 P02/AD2
59 P03/AD3
58 P04/AD4
57 P05/AD5
56 P06/AD6
55 P07/AD7
51 P27/A15
50 P26/A14
handbook, full pagewidth
P12 1 P13 2 P14 3 P15 4 P16 5 P17 6 RESET 7 RFU 8
49 P25/A13
52 PSEN
53 ALE
64 P11
63 P10
54 EA
48 P24/A12 47 P23/A11 46 P22/A10 45 P21/A9 44 P20/A8 43 DGND 42 VDDD 41 XTAL1
TDA8031
RFU 9 DELATT 10 RFU 11 SCANEN 12 I/O 13 RFU 14 C8 15 PRES 16 VCC 20 RST 21 TEST 22 VUP 23 LX 24 STGND 25 VDD 26 VDDU 27 UGND 28 D + 29 D- 30 CDELAY 31 P30/RxD 32 C4 17 CGND 18 CLK 19 40 XTAL2 39 P37/RD 38 P36/WR 37 P35 36 P34 35 P33/INT1 34 P32/INT0 33 P31/TxD
MGU884
Fig.4 Pin configuration (top view).
2003 Jul 04
12
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
8 FUNCTIONAL DESCRIPTION
TDA8030; TDA8031
The registers within the ISO7816 UART may be written to or read from by using the standard 83C51 MOVX instructions. It should be noted, that only if pin P27/A15 is HIGH, can the UART be accessed. When pin P27/A15 is HIGH, the demultiplexing of address and data is done internally by means of the ALE signal. A LOW pulse on pin P37/RD enables the selected register to be read, a LOW pulse on pin P36/WR enables the selected register to be written to. The ISO UART interrupt line is directly connected to the microcontrollers External Interrupt 0 input, pin P32/INT0. For that reason, the External Interrupt 0 of the 83C51 microcontroller must be enabled to ensure a proper function.
Throughout this specification, it is assumed that the reader is aware of ISO7816 and USB norms terminology. 8.1 ISO7816 UART AND ASSOCIATED LOGIC
This section describes how the integrated ISO7816 UART operates, how it can be programmed by means of its control registers and how it is internally interfaced to the embedded microcontroller. 8.1.1 INTERFACE CONTROL
The ISO7816 UART can be controlled via an 8-bit parallel bus. This bus is directly (internally) connected to Port 0 (P07 to P00) of the embedded 83C51 microcontroller.
handbook, full pagewidth ALE
CS
D0 to D7
address
data read
address
data write
RD
WR
MGU885
Fig.5 Control via MOVX instructions.
2003 Jul 04
13
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
8.1.2 CONTROL REGISTERS
TDA8030; TDA8031
The Hardware Status Register (HSR) gives the status of the supply voltage, of the hardware protections and of the card movements. The USR and HSR give interrupts on pins INT when some of their bits have been changed. The MSR does not give interrupts and may be used in the polling mode for some operations; when this is the case, the bit Transmit Buffer Empty/Receive Buffer Full (TBE/RBF) within the USR may be masked. A 24-bit time-out counter may be started to provide an interrupt after a number of ETUs programmed in time-out registers TOR1, TOR2 and TOR3. This will help the microcontroller when processing different real-time tasks (ATR, WWT and BWT etc.), mainly if the microcontrollers and cards clock are asynchronous. This counter is configured with a Time-Out Counter Configuration register (TOCC) and may be used as a 24-bit or as a 16 + 8-bit counter. Each counter may be set to start counting once data has been written, or on detection of a start bit on the I/O or as autoreload. 8.1.3 GENERAL REGISTERS
The TDA8030; TDA8031 has 1 analog interface for 7 contacts cards. The data to and from the cards is fed into an ISO UART. The Card Select Register (CSR) contains one bit for resetting the ISO UART (RIU, active LOW). This bit is reset after power-on and must be set HIGH before starting any operation. It may be reset by software when necessary. The following dedicated registers enable the parameters of the ISO UART and the ETU counters to be set: * Programmable Divider Register (PDR) * Guard Time Register (GTR) * Two UART Control Registers (UCR1 and UCR2) * Clock Configuration Register (CCR) * Time-Out Configuration Register (TOCR) * Three Time-Out Registers (TOR1, TOR2 and TOR3). There is also a dedicated Power Control Register (PCR) for controlling the power to the card. When the specific parameters of the card have been programmed, the UART may be used with the following registers: * UART Receive Register (URR) * UART Transmit Register (UTR) * UART Status Register (USR) * Mixed Status Register (MSR). In the reception mode, a FIFO of 1 to 8 characters may be used and is configured with the FIFO Control Register (FCR). This register may also be used for programming an automatic repetition of NAKed characters in the transmission mode. Table 1 7 - Note 1. All bits are cleared after reset.
8.1.3.1
Card select register
The Card Select Register (CSR) is used for resetting the ISO UART. The bit Reset ISO UART (RIU) must be set to logic 1 by software before any action on the UART. When set to logic 0, this bit resets a large part of the UART registers to their default value; see Table 1. A minimum pulse of 10 ns is needed on RIU. This bit must be reset before any new activation.
Card select register (address 00H; write and read); note 1 6 - 5 - 4 - 3 RIU 2 - 1 - 0 -
2003 Jul 04
14
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
8.1.3.2 Hardware status register
TDA8030; TDA8031
The Hardware Status Register (HSR) gives the status of the chip after a hardware problem has been detected. Table 2 7 - Note 1. All bits are cleared after reset. Table 3 BIT 7 and 6 5 4 3 2 1 0 Description of the HSR bits SYMBOL - PRTL SUPL - PRL - PTL not used Protection 1: Bit PRTL = 1 when a default has been detected on card reader. Bit PRTL is the OR function of the protection on pins VCC and RST. Supervisor Latch: Bit SUPL = 1 when the supervisor has been activated. not used Presence Latch: Bit PRL = 1 when a change has occurred on pin PRES. not used Overheating: Bit PTL = 1 if overheating has occurred. DESCRIPTION Hardware Status Register (address 0FH; read only); note 1 6 - 5 PRTL 4 SUPL 3 - 2 PRL 1 - 0 PTL
When either bits PRTL, PRL or PTL is logic 1, then pin INT0 is LOW. The bits having caused the interrupt are cleared when the HSR has been readout (2 x fint cycles after the rising edge of RD). At power-on, or after a supply voltage drop-out, SUPL is set and INT0 is LOW. INT0 will return HIGH at the end of the internal Power-on reset pulse defined by the value of the capacitor connected to pin CDELAY. SUPL will be reset only after a status register readout outside the Power-on reset pulse; see Fig.8. In the event of emergency deactivation (by PRTL, SUPL, PRL and PTL), bit START will be automatically reset by hardware.
8.1.3.3
Time-out registers
The three Time-Out Registers TOR1, TOR2 and TOR3 form a programmable 24-bit ETU counter, or two independant counters (one 16-bit and one 8-bit). The value to load in TOR1, TOR2 and TOR3 is the number of ETUs to count. Table 4 7 TOL7 Note 1. All bits are cleared after reset. Time-out register 1 (address 09H; write only); note 1 6 TOL6 5 TOL5 4 TOL4 3 TOL3 2 TOL2 1 TOL1 0 TOL0
2003 Jul 04
15
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
Table 5 7 TOL15 Note 1. All bits are cleared after reset. Table 6 7 TOL23 Note 1. All bits are cleared after reset. Time-out register 3 (address 0BH; write only); note 1 6 TOL22 5 TOL21 4 TOL20 3 TOL19 2 TOL18 Time-out register 2 (address 0AH; write only); note 1 6 TOL14 5 TOL13 4 TOL12 3 TOL11 2 TOL10
TDA8030; TDA8031
1 TOL9
0 TOL8
1 TOL17
0 TOL16
8.1.3.4
Time-out configuration register
The Time-Out Configuration register (TOCR) is used for setting different configurations of the time-out counter according to Table 8; all other configurations are undefined. The timers can operate in 3 modes: 1. Software triggered 2. Start bit triggered 3. Autoreload. Table 7 7 TOC7 Note 1. All bits are cleared after reset. Time-out configuration register (address 08H; read and write); note 1 6 TOC6 5 TOC5 4 TOC4 3 TOC3 2 TOC2 1 TOC1 0 TOC0
2003 Jul 04
16
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
Table 8 Time-out counter configuration OPERATING MODE All counters are stopped.
TDA8030; TDA8031
TOC VALUE 00H 05H 61H
Counters 2 and 3 are stopped; counter 1 continues to operate in autoreload mode. Counter 1 is stopped and counters 3 and 2 form a 16-bit counter. Counting the value stored in TOR3 and TOR2 is started after 6H is written in the TOCR. An interrupt is given and bit TO3 is set within the USR when the terminal count is reached. The counter is stopped by writing 00H in the TOCR and will be stopped before reloading a new value in TOR2 and TOR3. Counter 1 is an 8-bit autoreload counter and counters 3 and 2 form a 16-bit counter. Counter 1 starts counting the content of TOR1 on the first START bit (reception or transmission) detected on I/O after 65H is written in the TOCR. When Counter 1 reaches its terminal count, an interrupt is given, bit TO1 in the USR is set and the counter automatically restarts the same count until it is stopped. It is not allowed to change the content of TOR1 during a count. Counters 3 and 2 are wired as a single 16-bit counter and starts counting the value TOR3 and TOR2 when 65H is written in the TOCR. When the counter reaches its terminal count, an interrupt is given and bit TO3 is set within the USR. Both counters are stopped when 00H is written in the TOCR. Counters 3 and 2 will be stopped by writing 05H in the TOCR before reloading a new value in TOR2 and TOR3. Counters 3, 2 and 1 are wired as a single 24-bit counter. Counting the value stored in TOR3, TOR2 and TOR1 is started after 68H is written in the TOCR. The counter is stopped by writing 00H in the TOCR. It is not allowed to change the content of TOR3, TOR2 and TOR1 within a count. Counters 3, 2 and 1 are wired as a single 24-bit counter. Counting the value stored in TOR3, TOR2 and TOR1 on the first start bit detected on I/O (reception or transmission) after the value has been written. It is possible to change the content of TOR3, TOR2 and TOR1 during a count; the current count will not be affected and the new count value will be taken into account at the next start bit. The counter is stopped by writing 00H in the TOCR. In this configuration TOR3, TOR2 and TOR1 must not be all zero. Same as 05H, except that all the counters will be stopped at the end of the 12th ETU following the first received start bit detected after 85H has been written in the TOCR. Same configuration as TOCR = 65H, except that Counter 1 will be stopped at the end of the 12th ETU following the first start bit detected after E5H has been written in the TOCR. The minimum time interval between 2 successive write operations in TOCR is 231 or 232 ETU. It is obvious that the counters may only be used once the card has been activated. Detailed examples of how to use these specific timers can be found in Application Note "AN01012".
65H
68H
7CH
85H E5H
The time-out counter is very useful for processing the clock counting during ATR, the Work Waiting Time (WWT) or the waiting times defined in T = 1 protocol. The 200 and 384 clock counter used during ATR is done by hardware when Start Session is set, a specific hardware takes care of BGT in T = 1 protocol and a specific register is present for processing the extra guard time. It is not allowed to change the content of the TOR registers whilst a counter is in software triggered mode, or in autoreload mode. In these modes, it is mandatory to stop the counters (TOCR = 00H or 05H) before updating the count value in the TOR registers. In start bit triggered mode, the value may be changed at any time; the new count value will be taken into account on the next start bit.
2003 Jul 04
17
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
8.1.4 ISO UART REGISTERS
TDA8030; TDA8031
* Does not start if the transmission of the previous character is not completed. When the transmission is completed: * In T = 0, bit TBE is set at 11.5 ETU, and bit PE in the event of parity error * In T = 1, bit TBE is set at 10.5 ETU. In the event of synchronous cards (bit SAN set within UCR2), UT0 is only relevant and is copied on the I/O of the card. It is possible to write within the UTR before setting the transmission mode, which may be useful in some cases.
8.1.4.1
UART transmit register
When the microcontroller wants to transmit a character to the card, it writes the data in direct convention in this register. The transmission: * Starts at the end of this writing (2 clock cycles after the rising edge of WR) if the previous character has been transmitted and if the extra guard time has expired * Starts at the end of the extra guard time if this one has not expired * Starts at 13.5 ETU in manual mode and 15 ETU in automatic mode if the previous character has been NAKed by the card; see Section 8.1.4.4 Table 9 7 UT7 Note 1. All bits are cleared after reset.
UART transmit register (address 0DH; write only); note 1 6 UT6 5 UT5 4 UT4 3 UT3 2 UT2 1 UT1 0 UT0
8.1.4.2
UART receive register
When the microcontroller wants to read data from the card, it reads it from this register in direct convention. In the event of synchronous cards, only UR0 is relevant and is a copy of the state of the card I/O. In the event of parity error: * The bit PE in the status register USR is set at 10.5 ETU and INT0 falls LOW * In protocol T = 0, the received byte is not stored in URR; In protocol T = 1, the received byte is stored.
In both protocols, when a character has been stored, then the bit RBF in the status register USR is set at 10.5 ETU. This bit is reset when the character has been read from the URR. When the URR is empty, then bit FE (in the MSR) is set as long as no character has been received.
Table 10 UART receive register (address 0DH; read only); note 1 7 UR7 Note 1. All bits are cleared after reset. 6 UR6 5 UR5 4 UR4 3 UR3 2 UR2 1 UR1 0 UR0
2003 Jul 04
18
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
8.1.4.3 Mixed status register
TDA8030; TDA8031
The Mixed Status Register (MSR) relates the status of the cards presence contact PRES, the BGT counter, the FIFO empty indication, the transmit/receive ready indicator TBE/RBF and the completion of clock switching to or from 12fint. Table 11 Mixed status register (address 0CH; read only); note 1 7 CLKSW Note 1. Bits TBE/RBF are cleared after reset; bit FE is set after reset. Table 12 Description of the MSR bits; note 1 BIT 7 SYMBOL CLKSW DESCRIPTION Clock switch: Bit CLKSW = 1 when the TDA8030; TDA8031 has performed a required clock switch from 1nfxtal to 12fint and is reset when the TDA8030; TDA8031 has performed a required clock switch from 12fint to 1nfxtal; the application will wait until this bit has been set or reset before setting the microcontroller in power-down mode or restarting sending commands after leaving power-down mode (only needed when the clock is not stopped). This bit is also reset by RIU and at power-on. FIFO Empty: Bit FE = 1 when the reception FIFO is empty; it is reset when at least one character has been loaded in the FIFO. Block Guard Time: In T = 1 protocol, the bit BGT is linked with a 22 ETU counter, which is started at every start bit on the I/O. If the count is finished before the next start bit, then bit BGT is set. This helps to ensure that the card has not answered before 22 ETU after the last transmitted character, or that the reader is not transmitting a character before 22 ETU after the last received character. In T = 0 protocol, the bit BGT is linked to a 16 ETU counter, which is started at every start bit on the I/O. If the count is finished before the next start bit, then the bit BGT is set. This helps to ensure that the reader is not transmitting too early after the last received character. 4 and 3 2 1 0 PR - TBE/RBF not used Presence: Bit PR = 1 when the card is present. not used Transmit Buffer Empty/Receive Buffer Full: Bit TBE/RBF = 1 when: * Changing from reception mode to transmission mode * A character has been transmitted by the UART (except when a character has been transmitted free of parity error while LCT = 1) * The reception buffer is full. Bit TBE/RBF = 0 after power-on, or after one of the following: * When the bit RIU is reset * When a character has been written into register UTR * When the character has been read in register URR * When changing from transmission mode to reception mode. Note 1. No bits within the MSR have an effect on INT0. 2003 Jul 04 19 6 FE 5 BGT 4 - 3 - 2 PR 1 - 0 TBE/RBF
6 5
FE BGT
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
8.1.4.4 FIFO control register
TDA8030; TDA8031
The FIFO Control Register (FCR) relates the parity error count and the FIFO length. Table 13 FIFO control register (address 0CH; write only); note 1 7 - Note 1. All bits are cleared after reset. Table 14 Description of the FCR bits BIT 7 6 to 4 SYMBOL - PEC2 to PEC0 not used Parity Error Count: PEC2, PEC1 and PEC0 determine the number of parity errors before setting the bit PE within the USR and pulling INT0 LOW; 000 means that only one parity error has occurred and bit PE is set. The value 000 indicates that if only one parity error has occurred bit PE is set; the value 111 indicates that PE will be set after 8 parity errors. In protocol T = 0: * If a correct character is received before the programmed error number is reached the error counter will be reset * If the programmed number of allowed parity errors is reached, bit PE in the USR will be set as long as the USR has not been read * If a transmitted character has NAKed by the card, then the TDA8030; TDA8031 will automatically re-transmit it a number of times equal to the value programmed in PEC2, PEC1 and PEC0. The character will be resent at 15 ETU * In transmission mode, if bits PEC2, PEC1 and PEC0 are at logic 0, then the automatic re-transmission is invalidated; the character manually rewritten in the UTR will start at 13.5 ETU. In protocol T = 1: * The error counter has no action; bit PE is set at the first incorrectly received character. 3 2 to 0 - FL2 to FL0 not used FIFO Length: Bits FL2, FL1 and FL0 determine the depth of the FIFO: * 000 = length 1 * 111 = length 8 DESCRIPTION 6 PEC2 5 PEC1 4 PEC0 3 - 2 FL2 1 FL1 0 FL0
2003 Jul 04
20
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
8.1.4.5 UART status register
TDA8030; TDA8031
The UART Status Register (USR) is used by the microcontroller to monitor the activity of the ISO UART and of the time-out counter. Table 15 UART status register (address 0EH; read only); note 1 7 TO3 Note 1. All bits are cleared after reset. Table 16 Description of the USR bits BIT 7 6 5 4 SYMBOL TO3 - TO1 EA DESCRIPTION Time-Out counter 3: Bit TO3 = 1 when counter 3, or counters 3 + 2 or counters 3 + 2 + 1 have reached their terminal count. not used Time-Out counter 1: Bit TO1 = 1 when counter 1 has reached its terminal count. Early Answer: When bit RST is LOW, EA is HIGH if the first start bit on the I/O during ATR has been detected between 200 and 384 clock pulses (all activities on the I/O during the first 200 clock pulses with RST LOW are not taken into account). When RST is HIGH, EA is HIGH if a start bit has been detected before the 384th clock pulse. These two features are reinitialized at each toggling of RST. Parity Error: In T = 0 protocol, PE = 1 if the UART has detected a number of received characters with parity error equal to the number written in PEC2, PEC1 and PEC0 or if a transmitted character has been NAKed by the card a number of times equal to the value programmed in PEC2, 1 and 0. It is set at 10.5 ETU in reception mode and at 11.5 ETU in transmission mode. In T = 0 protocol, a character received with a parity error is not stored in the FIFO, the card is supposed to repeat this character. In T = 1 protocol, a character with a parity error is stored in the FIFO and the parity error counter is not operating. 2 1 0 OVR FER TBE/RBF Overrun: Bit OVR = 1 if the UART has received a new character while the URR was full. In this case, at least one character has been lost. OVR is set at 10.5 ETU. Framing Error: Bit FER = 1 when the I/O was not in high-impedance state at 10.25 ETU after a start bit. It is reset when the USR has been read-out. Transmission Buffer Empty/Reception Buffer Full: Bits TBE and RBF share the same bit within the USR. When in transmission mode the relevant bit is TBE; when in reception mode it is RBF. Bit TBE = 1 when the UART is in transmission mode and when the microcontroller may write the next character to transmit in the UTR. It is reset when the microcontroller has written data in the Transmit Register, or when the bit T/R within UCR1 has been reset either automatically or by software. TBE is set at 11.5 ETU in T = 0 protocol and at 10.5 ETU in T = 1 protocol. Bit RBF = 1 when the FIFO is full. The microcontroller may read some of the characters in the URR, which clears the bit RBF. Bit RBF is also reset when entering the reception mode and is set at 10.5 ETU. 6 - 5 TO1 4 EA 3 PE 2 OVR 1 FER 0 TBE/RBF
3
PE
2003 Jul 04
21
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
If any of the status bits FER, OVR, PE, EA, TO1 or TO3 are set, then INT0 is LOW. The bit having caused the interrupt is reset 2 x fint cycles after the rising edge of RD during a read operation of the USR. If TBE/RBF is set and if the mask bit DISTBE/RBF within UCR2 is not set, then INT0 is also LOW. TBE/RBF is reset 2 clock cycles after data has been written into the UTR, or 2 clock cycles after data has been read from the URR, or when changing from transmission mode to reception mode if the FIFO had not been left full when going to transmission mode. If the Last Character to Transmit (LCT) is used for transmitting the last character, then TBE will not be set at the end of the transmission. 8.1.5
TDA8030; TDA8031
CARDS REGISTERS
When working with a card, the following registers may be used for programming some specific parameters:
8.1.5.1
Programmable divider register
The Programmable Divider Register (PDR) is used for counting the cards clock cycles which form the ETU. It is an autoreload 8-bit counter decounting from the programmed value down to 0.
Table 17 Programmable divider register (address 02H; read and write); note 1 7 PD7 Note 1. All bits are cleared after reset. 6 PD6 5 PD5 4 PD4 3 PD3 2 PD2 1 PD1 0 PD0
8.1.5.2
UART configuration register 2
Table 18 UART configuration register 2 (address 03H; read and write); note 1 27 ENINT1 Note 1. All bits are cleared after reset. 26 DISTBE/ RBF 25 - 24 - 23 SAN 22 AUTOCONV 21 CKU 20 PSC
2003 Jul 04
22
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
Table 19 Description of the UCR2 bits BIT 27 SYMBOL ENINT1 DESCRIPTION
TDA8030; TDA8031
Enable Interrupt 1: If bit ENINT1 = 1, then a HIGH-to-LOW transition on INT1 will wake-up the microcontroller from power-down mode. When not in power-down mode, bit ENINT1 has no effect. Disable TBE/RBF interrupts: If bit DISTBE/RBF = 1, then reception or transmission of a character will not generate an interrupt. This feature is useful for increasing communication speed with the card; in this case, the copy of TBE/RBF bit within the MSR must be polled and not the original, in order not to loose priority interrupts which can occur in the USR. not used not used Synchronous/Asynchronous: Bit SAN is set by software if a synchronous card is expected. Then, the UART is bypassed and only bit 0 in the URR and UTR is connected to the I/O. In this case, the clock is controlled by bit SC in the CCR.
26
DISTBE/ RBF
25 24 23
- - SAN
22
AUTOCONV Auto convention: If bit AUTOCONV = 1, then the convention is set by software with bit CONV in the UART Configuration Register. If it is reset, then the configuration is automatically detected on the first received character while the bit SS (Start Session) is set. CKU Clock UART: Bit CKU is used to clock the UART at twice the clock frequency of the card. An ETU will last 31 x PDR clock pulses if CKU = 0 and half if CKU = 1. It should be noted that when CKU = 1 it has no effect if fCLK = fXTAL1. This means, for example, that a baud rate of 76800 is not possible when the card is clocked with the frequency on XTAL1. Prescaler: If bit PSC = 1, then the prescaler value is 32. If PSC = 0, then the prescaler value is 31. One ETU will last a number of cards clock cycles equal to PSC x PDR. All baud rates specified in "ISO7816" norm are achievable with this configuration.
21
20
PSC
handbook, full pagewidth
CLK MUX 2 x CLK CKU
/ 31 or 32
PSC
/ PDR
MGU886
ETU
Fig.6 ETU generation.
2003 Jul 04
23
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
8.1.5.3
TDA8030; TDA8031
Baud rate selection using F and D; card clock frequency fCLK = 3.58 MHz for PSC = 31 and 4.92 MHz for PSC = 32 (31;12 means prescaler set to 31 and PDR set to 12)
F
D 0 1 2 3 4 5 6 8 9 31;1 31;1 115200 115200 31;2 31;3 57600 38400 31;4 28800 31;5 23040 31;3 38400 32;2 76800 31;12 9600 31;6 19200 31;3 38400 1 31;12 9600 31;6 19200 31;3 38400 2 31;18 6400 31;9 12800 3 31;24 4 800 31;12 9600 4 31;36 3200 31;18 6400 5 31;48 2400 31;24 4800 31;12 9600 31;6 19200 31;3 38400 6 31;60 1920 31;30 3840 31;15 7680 9 32;16 9600 32;8 19200 32;4 38400 32;2 76800 32;1 153600 10 32;24 6400 32;12 12800 32;6 25600 32;3 51300 11 32;32 4800 32;16 9600 32;8 19200 32;4 38400 32;2 76800 32;1 153600 32;4 38400 12 32;48 3200 32;24 6400 32;12 12800 32;6 25600 32;3 51300 13 32;64 2400 32;32 4800 32;16 9600 32;8 19200 32;4 38400 32;2 76800
31;6 31;9 19200 12800 31;3 38400
8.1.5.4
Guard time register
The Guard Time Register (GTR) is used for storing the number of guard ETUs given by the card during ATR. In transmission mode, the UART will wait this number of ETU + 0.5 before transmitting the character stored in UTR. In T = 1 protocol, GTR = FFH means operation at 11.5 ETU. In T = 0 protocol and GTR = FFH means operation at 12.5 ETU. Table 20 Guard time register (address 05H; read and write); note 1 7 GT7 Note 1. All bits are cleared after reset. 6 GT6 5 GT5 4 GT4 3 GT3 2 GT2 1 GT1 0 GT0
8.1.5.5
UART configuration register 1
The UART Configuration Register 1 (UCR1) is used for setting the parameters of the ISO UART. Table 21 UART configuration register 1 (address 06H; read and write); note 1 7 - Note 1. All bits are cleared after reset. 6 FIP 5 FC 4 PROT 3 T/R 2 LCT 1 SS 0 CONV
2003 Jul 04
24
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
Table 22 Description of the UCR1 bits BIT 7 6 5 4 3 SYMBOL - FIP FC PROT T/R not used DESCRIPTION
TDA8030; TDA8031
Force Inverse Parity: If FIP = 1, then the UART will NAK a correct received character and will transmit characters with wrong parity bit. Bit FC is a test bit and must be left at logic 0. Protocol: Bit PROT = 1 if the protocol type is asynchronous T = 1. If PROT = 0, the protocol is T = 0. Transmit/Receive: Bit T/R is set by software for transmission mode. A change from 0 to 1 will set bit TBE in the USR. T/R is automatically reset by hardware if LCT has been used before transmitting the last character. Last Character to Transmit: Bit LCT is set by software before writing the last character to transmit into the UTR. It allows automatic change to reception mode when reset by hardware at the end of a successful transmission (11 + 2831 or 2832 ETU in T = 0 and 10 + 2831 or 2832 ETU in T = 1). When LCT is being reset, the bit T/R is also reset and the UART is then ready for receiving a character. Start Session: Bit SS is set by software before ATR for automatic convention detection and early answer detection. It is automatically reset by hardware at 10.5 ETU after reception of the initial character. Convention: Bit CONV = 1 if the convention is direct. CONV is either automatically written to by hardware, according to the convention detected during ATR, or by software if bit AUTOCONV is set.
2
LCT
1
SS
0
CONV
8.1.5.6
Clock configuration register
The Clock Configuration Register (CCR) defines the clock to the card and the clock to the ISO UART. If bit CKU in the Prescaler Register (UCR2) of the card is set, then the ISO UART is clocked at twice the frequency to the card, this allows higher baud rates to be reached than foreseen in the ISO7816 norm. Table 23 Clock configuration register (address 01H; read and write); note 1 7 - Note 1. All bits are cleared after reset. 6 - 5 SHL 4 CST 3 SC 2 AC2 1 AC1 0 AC0
2003 Jul 04
25
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
Table 24 Description of the CCR bits BIT 7 6 5 SYMBOL - - SHL not used not used DESCRIPTION
TDA8030; TDA8031
Stop HIGH or LOW: If bit CST = 1, then the clock is stopped at LOW level if SHL = 0 and at HIGH level if SHL = 1. In these modes, the bias current in the card drivers is reduced; the current drawn by the card (ICC) should be less than 10 mA at all VCC voltages. Clock stop: In case of asynchronous cards, bit CST defines whether the clock to the card is stopped or not. If bit CST is reset, then the clock is determined by bits AC0, AC1 and AC2; see Table 25. All frequency changes are synchronous, thus ensuring that no spike or unwanted pulse widths occurs during changes. Synchronous Clock: In the event of synchronous cards, the clock contact is a copy of the value written in SC. In reception mode, the data from the card is available in bit UR0 after a read operation of the URR register. In transmission mode, bit UT0 is written on the I/O line of the card when UTR register has been written. When switching from 1nfxtal to 12fint or vice versa, only bit AC2 must be changed; AC1 and AC0 must remain the same. When switching from 1nfxtal or 12fint to CLK STOP or vice versa, only bits CST and SHL must be changed. When switching from 1nfxtal to 12fint or vice versa, a maximum delay of 200 s can occur between the command and the effective frequency change on pin CLK. The fastest switch is from 12fxtal to 12fint or vice versa, the best duty cycle is from 18fxtal to 12fint or vice versa. The status bit CLKSW within the MSR gives the effective switch moment.
4
CST
3
SC
2 to 0
AC2 to AC0
Table 25 CLK value for an asynchronous card AC2 0 0 0 0 1 1 1 1 Note 1. If fCLK = fXTAL, the duty cycle must be ensured by the incoming clock signal on XTAL1. AC1 0 0 1 1 0 0 1 1 AC0 0 1 0 1 0 1 0 1 CLK(1) fxtal 1 f 2 xtal 1 f 4 xtal 1 f 8 xtal 1 f 2 int 1 f 2 int 1 f 2 int 1 f 2 int
2003 Jul 04
26
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
8.1.5.7 Power control register
TDA8030; TDA8031
The Power Control Register (PCR) performs two tasks: 1. Starts or stops card sessions 2. Reads from or writes to auxiliary card contacts C4 and C8. Table 26 Power control register (address 07H; read and write); note 1 7 - Note 1. All bits are cleared after reset. Table 27 Description of the PCR bits BIT 7 6 5 4 3 2 1 0 SYMBOL - - C8 C4 1.8V RSTIN 3/5V START not used not used Contact 8: When writing to the PCR bit C8 will output the value of bit C8. When reading from the PCR, bit C8 will store the value on pin C8. Contact 4: When writing to the PCR bit C4 will output the value written of bit C4. When reading from the PCR bit C4 will store the value on pin C4. 1.8 V cards: if bit 1.8V is set, then VCC = 1.8 V. Reset bit: When the card is activated, pin RST is the copy of the value written in RSTIN. 3 or 5 V cards: If bit 3/5V is set to logic 1, then VCC is 3 V; If bit 3/5V is set to logic 0, then VCC is 5 V. Start: If the microcontroller sets bit START to logic 1, then the selected card is activated; see Section 8.3.3. If the microcontroller resets START to logic 0, then the card is deactivated; see Section 8.3.4. START is automatically reset in the event of emergency deactivation. For deactivating the card, only bit START should be reset. DESCRIPTION 6 - 5 C8 4 C4 3 1.8V 2 RSTIN 1 3/5V 0 START
2003 Jul 04
27
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 8.1.6 NAME CSR CCR PDR UCR2 GTR UCR1 PCR TOC TOR1 TOR2 TOR3 MSR 28 FCR UTR URR USR HSR REGISTERS SUMMARY 2003 Jul 04 Philips Semiconductors
USB smart card reader (OTP or ROM)
ADDR 00H 01H 02H 03H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0CH 0DH 0DH 0EH 0FH
R/W R/W R/W R/W R/W R/W R/W R/W R/W W W W R W W R R R
7 - - PD7 ENINT1 GT7 - - TOC7 TOL7 TOL15 TOL23 CLKSW - UT7 UR7 TO3 -
6 - - PD6 DISTBE/ RBF GT6 FIP - TOC6 TOL6 TOL14 TOL22 FE PEC2 UT6 UR6 - -
5 - SHL PD5 - GT5 FC C8 TOC5 TOL5 TOL13 TOL21 BGT PEC1 UT5 UR5 TO1 PRTL
4 - CST PD4 - GT4 PROT C4 TOC4 TOL4 TOL12 TOL20 - PEC0 UT4 UR4 EA SUPL
3 RIU SC PD3 SAN GT3 T/R 1.8 V TOC3 TOL3 TOL11 TOL19 - - UT3 UR3 PE -
2 - AC2 PD2 AUTOCO NV GT2 LCT RSTIN TOC2 TOL2 TOL10 TOL18 PR FL2 UT2 UR2 OVR PRL
1 - AC1 PD1 CKU GT1 SS 3/5 V TOC1 TOL1 TOL9 TOL17 - FL1 UT1 UR1 FER -
0 - AC0 PD0 PSC GT0 CONV START TOC0 TOL0 TOL8 TOL16 TBE/RBF FL0 UT0 UR0 TBE/RBF PTL
VALUE AT RESET XXXX0XXX XX000000 00000000 00XX0000 00000000 X0000000 XX110000 00000000 00000000 00000000 00000000 010XXXX0 X000X000 00000000 00000000 0X000000 XX01X0X0
VALUE WHEN RIU = 0 XXXX0XXX XX000000 00000000 00XX0000 00000000 X0000000 XX110000 00000000 00000000 00000000 00000000 010XXXX0 X000X000 00000000 00000000 00000000 XX01X0X0
TDA8030; TDA8031
Product specification
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
8.2 SUPPLY
TDA8030; TDA8031
For programming the EPROM of the TDA8030; TDA8031, by applying a logic 1 to pin CPROG it will disable the regulator, so that the microcontroller will be powered-up at 5 V. 8.2.3 DC-TO-DC CONVERTER
The supply to the chip is delivered by the USB-bus (pins VDDU and UGND). 8.2.1 POWER SWITCH CONTROL
A power switch control is used in order to limit the inrush current when plugging the reader into the bus. The main decoupling capacitor is connected to the output of this power switch control (pin VDD). 8.2.2 3.3 V REGULATOR
In case of a 5 V card, the card buffers are supplied by an inductive DC-to-DC converter. In case of a 3 or 1.8 V card, the DC-to-DC converter is transparent and the card buffers are then supplied directly by VDD. The external components for the DC-to-DC converter should be an inductance of 6.8 H, a low ESR capacitor of 1 F and a Schottky diode (type BAT54). The power efficiency is approximately 85% up to ICC = 55 mA. The current is limited at 100 mA during the start-up phase to avoid spurious supply drop-outs. The DC-to-DC converter is transparent for a 3 V card.
The output voltage of the 3.3 V linear regulator is used for: * Powering-up the microcontroller and the ISO7816 UART * It is the reference voltage for the signalling pull-up resistor connected to pin D+. If this voltage is used within the application, the current should not exceed 10 mA. For stability reasons, a 1 F low ESR decoupling capacitor is needed between the output of the regulator (VDDD) and the specific regulator ground (DGND).
handbook, full pagewidth
VDD
LX
VUP
clock
N drive
reset low up
P drive
Vref
MGU887
Fig.7 DC-to-DC converter.
2003 Jul 04
29
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
8.2.4 SUPPLY SUPERVISOR
TDA8030; TDA8031
This pulse is used as a Power-on reset pulse and also to either block any spurious spikes on card contacts during microcontrollers reset, or to force an automatic deactivation of the contacts in the event of supply drop-out; see Sections 8.3.3 and 8.3.4. After power-on, or after a voltage drop, bit SUPL is set within the Hardware Status Register (HSR) and remains set until HSR is readout outside the alarm pulse. As long as the Power-on reset is active, INT0 is LOW. The same events occurs when the RESET pin has been set active; the RESET pin should be set HIGH for a minimum of 100 s for a proper reset.
The switched supply voltage (VDD) is surveyed by a voltage supervisor, to ensure proper Power-on reset when the reader is plugged into the USB-bus, to maintain all cards contacts inactive during power-on and also to enforce an emergency deactivation sequence in case of VDD drop-out or when the reader is unplugged from the USB-bus. The voltage supervisor generates an alarm pulse, whose length is defined by an external capacitor tied to the CDELAY pin, when VDD is too low to ensure proper operation (1 ms per 2 nF typical).
handbook, full pagewidth
supply dropout
reset by pin RESET
Vth1 VDD Vth2 CDELAY
RESET tw SUPL tw tw
INT0
MGU888
power-on
status read
power- off
Fig.8 Voltage supervisor.
2003 Jul 04
30
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
8.3 8.3.1 ISO7816 SECURITY INTRODUCTION 8.3.3
TDA8030; TDA8031
ACTIVATION SEQUENCE
The correct sequence during activation and deactivation of the cards is ensured through a specific sequencer, clocked by a division ratio of the internal oscillator. Activation (START bit HIGH in the Power Control Register) is only possible if the card is present (PRES active HIGH) and if the supply voltage is correct (supervisor not active). The presence of the card is signalled to the microcontroller by the Hardware Status Register (HSR). Bit PRL in the HSR is set if the card is present. Bit PRL in the HSR is set if bit PRL has toggled. During a session, the sequencer performs an automatic emergency deactivation on the card in the event of card take off, a short-circuit, a supply drop-out or overheating. When the HSR register is updated and the INT0 line goes LOW, the microcontroller will also be updated. 8.3.2 PROTECTIONS AND LIMITATIONS
When the card is inactive, VCC, CLK, RST, I/O, C4 and C8 are LOW, with low-impedance with referenced to CGND. The DC-to-DC converter is stopped. When everything is in normal conditions (no error flag set), the microcontroller will initiate an activation sequence of the card. After leaving the UART reset mode and then configuring the necessary parameters for the UART, the START bit in the PCR (t0) will be activated. The following sequence then occurs: 1. The DC-to-DC converter is started (t1) 2. VCC starts rising from 0 to 5 V or 3 or 1.8 V with a controlled rise time of 0.17 V/s typically (t2) 3. I/O, C4 and C8 rise to VCC (t3); integrated 10 k pull-up resistors connected to VCC 4. Clock pulses are sent to the card and RST is enabled (t4). After a number of clock pulses that can be counted with the Time-Out Counter, the bit RSTIN may be set by software and RST will rise to VCC. The sequencer is clocked by 164fint which leads to a time interval of t = 25 s typical. Thus t1 = 0 to 364t, t2 = t1 + 52t, t3 = t1 + 92t and t4 = t1 + 5t.
The TDA8030; TDA8031 features the following protections and limitations: 1. ICC limited to 100 mA, deactivated when this limit is reached 2. Current to and from RST is limited to 20 mA, deactivated when this limit is reached 3. Deactivation when the temperature of the die exceeds 150 C 4. Current to and from the I/O is limited to 10 mA 5. Current to and from pin CLK is limited to 70 mA (not in current reduction modes, when clock is stopped) 6. ESD protection on all cards contacts + PRES at 6 kV (min.), thus no need of extra components for protection against ESD flash caused by a charged card being introduced in the slot 7. Short-circuit between any cards contacts can last any duration without any damage.
2003 Jul 04
31
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
handbook, full pagewidth
START
VUP
VCC
I/O
CLK
RST
t0 t1
t2
t3
t 4 = t act
ATR
MGU889
Fig.9 Activation sequence.
8.3.4
DEACTIVATION SEQUENCE
When the session is completed, the microcontroller resets START (t10). The circuit then executes an automatic deactivation sequence as follows: 1. Card reset (RST falls LOW; t11) 2. Clock (CLK) is stopped LOW (t12) 3. I/O, C4 and C8 fall to 0 V (t13) 4. VCC falls to 0 V with typical 0.17 V/s slew rate (t14) 5. The DC-to-DC converter is stopped and CLK, RST, VCC, I/O, C4 and C8 become low-impedance to CGND (t15). Thus: t11 = t10 + 164t t12 = t11 + 12t t13 = t11 + t t14 = t11 + 32t t15 = t11 + 72t tde = time that VCC needs to decrease to less than 0.3 V.
Automatic emergency deactivation is performed in the following cases: 1. Withdrawal of the card (PRES LOW) 2. Overcurrent detection on VCC (bit PRTL set) 3. Overcurrent detection on RST (bit PRTL set) 4. Overheating (bit PTL set) 5. Supply too low (bit SUPL set) 6. RESET pin active HIGH. In all of these cases, the deactivation sequence as described above occurs. If the reason for the deactivation is a card take-off, an overcurrent or overheating, then INT0 will be LOW and the corresponding bit in the Hardware Status Register will be set. The START bit is automatically reset. If the reason is a supply drop-out, then the deactivation sequence occurs and a complete reset of the chip is performed. When the supply recovers, then the SUPL bit will be set in the HSR.
2003 Jul 04
32
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
handbook, full pagewidth
START
RST
CLK
I/O
VCC
VUP t de t 10 t 11 t 12 t 13 t 14 t 15
MGU890
Fig.10 Deactivation sequence.
2003 Jul 04
33
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
8.4 MICROCONTROLLER
TDA8030; TDA8031
The 80C51 microcontroller has four 8-bit I/O ports, three 16-bit timer/event counters, a multi-source, 4-level priority nested interrupt structure, an enhanced UART and on-chip oscillator and timing circuits. For systems that require extra memory capability up to 64 kbytes, it can be expanded by using standard TTL compatible memories and logic. 1. 80C51 Central Processing Unit (CPU) 2. Full static operation 3. Security bits: ROM 2 bits 4. Encryption array of 64 bits 5. 4-level priority structure 6. 6 interrupt sources 7. Full duplex enhanced UART with framing error detection and automatic address recognition 8. Power control modes (the clock can be stopped and resumed in IDLE mode and power-down mode) 9. Wake-up from power-down by a falling edge on pins INT0 and INT1; with an embedded delay counter 10. Programmable clock output 11. Second DPTR register 12. Asynchronous port reset 13. Low EMI (inhibit ALE). Table 28 gives a list of main features to get a better understanding of the differences between a standard 80C51, an 8XC51RB+ and the embedded microcontroller in the TDA8030; TDA8031.
The embedded microcontroller is an 80C51RB+ with an internal 16 kbyte EPROM (80C51FB with 16 kbyte ROM for the TDA8031), 256 RAM and 512 AUXRAM. It has the same instruction set as the 80C51. The embedded microcontroller is clocked by the frequency present on pin XTAL1. The embedded microcontroller may be reset by an active HIGH signal on pin RESET, but it is also reset by the Power-on reset signal generated by the voltage supervisor. The external interrupt INT0 is used by the ISO UART, by the analog drivers and by the ETU counters. It must be left open-circuit in the application. The external interrupt INT1 is used by the USB interface. It must be left open-circuit in the application. A general description, together with the added features, is described below. The added features to the 80C51 microcontroller are similar to the 8XC51FB/RB+ microcontrollers, except for the wake-up from power-down mode, which is enabled by a falling edge on pin INT0 (card reader event) or on pin INT1 due to the addition of an extra delay counter and enable configuration bits within the UCR2 register; see Section 8.4.1. For further information please refer to the published specification of the 8xC51RB + /FB in "Data Handbook IC20; 80C51-Based 8-bit Microcontrollers".
Table 28 Principal blocks in the 80C51, 8XC51RB+ and the TDA8030; TDA8031 FEATURE ROM/EPROM RAM ERAM (MOVX) PCA WDT T0 T1 T2 4 level priority interrupt enhanced UART delay counter 80C51 4 kbytes 128 bytes no no no yes yes no no no no 8XC51RB+ 16 kbytes 256 bytes 256 bytes yes yes yes yes yes yes yes no TDA8030; TDA8031 16 kbytes 256 bytes 512 bytes no no yes yes yes yes yes yes
lowest interrupt priority vector at 002BH
2003 Jul 04
34
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
8.4.1 LOW POWER MODES
TDA8030; TDA8031
The bits in the Interface Engine (IE) must be enabled with INT0 and INT1. Within the INT0 interrupt service routine, the microcontroller has to read out the Hardware Status Register (HSR at 0FH) and/or the UART Status register (USR at 0EH) by means of MOVX instructions in order to establish the exact interrupt reason and to reset the interrupt source. For enabling a wake-up by INT1, the bit ENINT1 within UCR2 must be set. An integrated delay counter maintains INT0 and INT1 LOW long enough to allow the oscillator to restart properly. A falling edge on pins INT0 and INT1 is enough to awaken the whole circuit. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put the device into power-down. 8.5 8.5.1 USB INTERFACE END-POINTS
Stop Clock Mode: The static design enables the clock speed to be reduced down to 0 MHz (stopped). When the oscillator is stopped, the RAM and Special Function Registers (SFRs) retain their values. This mode allows step-by-step utilization and permits reduced system power consumption by lowering the clock frequency down to any value. The power-down mode is suggested for the lowest power consumption. IDLE Mode: In the Idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the Idle mode is the last instruction executed in the normal operating mode before the Idle mode is activated. The CPU contents, the on-chip RAM and all of the special function registers remain intact during this mode. The Idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a Power-on reset. Power-down Mode: To save even more power, a power-down mode can be invoked by software. In this mode, the oscillator is stopped and the instruction that invoked the power-down is the last instruction executed. Either a hardware reset or external interrupt can be used to exit from the power-down mode. Applying a reset redefines all of the SFRs but does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values.
The TDA8030; TDA8031 has 4 logic end-points which are listed in Table 29. Each physical end-point, except for the control ones, can be enabled or disabled. All enabled end-points generate interrupts to the microcontroller via INT1 when the end-point needs to be serviced. The implementation of the function makes use of an SRAM for buffering the data. Logic end-points can be accessed by the microcontroller interface.
Table 29 Mapping of logic to physical end-point numbers for used end-points END-POINT NAME Control end-point Generic end-point (may be used as bulk Generic end-point (may be used as interrupt) Generic end-point LOGIC END-POINT 0 1 2 3 PHYSICAL END-POINT BUFFER SIZE OUT 16 32 8 8 0 2 - - IN 1 3 4 5
2003 Jul 04
35
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
8.5.2 PHASE-LOCKED LOOP
TDA8030; TDA8031
A 12 to 48 MHz clock multiplier PLL is integrated on-chip. No external components are needed for the operation of the PLL. 8.5.3 BIT CLOCK RECOVERY
The bit clock recovery circuit recovers the clock from the incoming USB data stream using 4x oversampling principle. It is able to track jitter and frequency drift as specified by the USB specification. 8.5.4 INTERFACE SIGNALS WITH THE MICROCONTROLLER
Table 30 The following I/O ports of the 83C51 are used for controlling the USB bus: PORT P10 P11 P12 P13 P14 P15 P33 P34 P35 P25 P26 8.5.5 FUNCTION USB_INT_MASK USB_SOFTCONNECT_INT USB_MC_READY USB_CLK_EN_N USB_RESET_N USB_SOFTCONNECT_EXT USB_INT_N USB_SUSPEND USB_WAKEUP_N USB_MP_C USB_MP_SEL BLOCK DIAGRAM DESCRIPTION should be set to logic 1 before entering power-down mode during suspend and reset to logic 0 when leaving power-down mode when set to logic 1, the internal 1.5 k resistor is connected to pin D+ the device is ready to accept a new transaction when LOW, this signal indicates that the bus is no longer suspended a LOW-level will reset the USB interface when set to logic 1, VDDD is applied on the optional external 1.5 k resistor which has been placed between pins D+ and DELATT interrupt to the microcontroller the device is in suspended state (TDA8030 only) remote wake-up (TDA8030 only) if set to logic 1, the data to the bus is a command; if set to logic 0 it is data if set to logic 1, the USB interface is selected
The digital interface consists of 3 major blocks: * The Philips Serial Interface Engine (SIE) handles the USB protocol (i.e. synchronization pattern, recognition, parallel/serial conversion, bit stuffing/de-stuffing, CRC checking/generating, PID verification/generation, address recognition and handshake evaluation/generation) * A Memory Management Unit (MMU), controlling the buffering of data to and from the bus * An interface to the embedded 83C51 microcontroller.
handbook, full pagewidth
OSCILLATOR
RAM
D+ USB bus D-
ANALOG TRANSCEIVER
SERIAL INTERFACE ENGINE
MEMORY MANAGEMENT UNIT
MICROCONTROLLER INTERFACE
MICROCONTROLLER
MGU891
Fig.11 USB block diagram.
2003 Jul 04
36
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
8.5.6 USB REGISTERS 8.5.7
TDA8030; TDA8031
INSTRUCTION SET
A first MOVX@DPTR instruction enables the module to be selected (via DPH) and send the command. A second one communicates the data (read or write). Table 31 Instruction set COMMAND NAME RECIPIENT
8.5.7.1
Overview
Table 31 summarizes all commands that can be used by the embedded microcontroller.
CODING
FUNCTION
DATA PHASE
Device commands; see Table 32 Set address Set end-points enable Set mode Read interrupt register Read current frame number Read chip ID Get device status Set device status Debug command: get error code Select end-point device device device device device device device device device 0XD0H 0XD8H 0XF3H 0XF4H 0XF5H 0XFDH 0XFEH 0XFEH 0XFFH set address set EP enable set mode write 1 byte write 1 byte write 1 byte read 1 byte read 1 or 2 bytes read 2 bytes read 1 byte write 1 byte read 1 byte
End-point commands; see Table 41 control output control input end-point 1 output end-point 1 input end-point 2 input 0X00H 0X01H 0X02H 0X03H 0X04H 0X05H 0X40H 0X41H 0X42H 0X43H 0X44H 0X45H 0X40H 0X41H 0X42H 0X43H 0X44H 0X45H 0XF0H 0XF0H 0XF2H 0XFAH select EP0 output select EP0 input read 1 byte (optional) read 1 byte (optional) read 1 byte (optional) read 1 byte (optional) read 1 byte (optional) read 1 byte (optional) read 1 byte read 1 byte read 1 byte read 1 byte read 1 byte read 1 byte write 1 byte write 1 byte write 1 byte write 1 byte write 1 byte write 1 byte read n + 2 bytes write n + 2 bytes read 1 byte (optional) none
end-point 3 input Select end-point/clear control output interrupt control input end-point 1 output end-point 1 input end-point 2 input end-point 3 input control output control input end-point 1 output end-point 1 input end-point 2 input end-point 3 input Read buffer Write buffer Clear buffer Validate buffer selected end-point selected end-point selected end-point selected end-point
Set end-point status
2003 Jul 04
37
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
Table 32 Device commands COMMAND Set address DESCRIPTION
TDA8030; TDA8031
The set address command is used to set the USB assigned address and to enable the function. In the event that the status phase of the set address transaction is not successful, the device address will not be updated. The power-on value is given in Table 33. A value of 1 written to the register indicates that the non-control end-points are enabled. The power-on value is given in Table 34. The default value is logic 0; if logic 1 is written in this register, then NAKing is reported and will generate an interrupt. When set to logic 0, only successful transactions are reported. This command indicates the origin of an interrupt. The end-point interrupt bits are cleared by the Select end-point/Clear Interrupt command. The power-on value is given in Table 35. The Read Current Frame Number returns the frame number of the last received Start Of Frame (SOF). The frame number is eleven bits wide. The frame number is returned LSB first, so, if the user is only interested in the lower 8 bits of the frame number, only the first byte needs to be read; see Table 36. The frame number returned by this commend can be invalid in the event of one of the following conditions: * If no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF * If the SOF frame number contained a CRC error, the frame number received will be the corrupted frame number as received by the device.
Set end-points enable Set Mode Read interrupt register Read Current Frame Number
Read chip ID Get Device Status Set Device Status Debug command: Get Error Code
The chip Identification is 16 bits wide. The command divides the ID into bytes and returns the least significant byte first: For the TDA8030; TDA8031, the ID is fixed at 2B00H. The Get Device Status command returns the Device Status Register; refer to the Set Device Status command The Set Device Status command sets bits in the Device Status Register. In Table 37, the Type column indicates if the bit can be written and if the bit is cleared after reading the register. The Interrupt column indicates if the bit generates an interrupt when it is set. The Get Error Code command returns the error code of the last generated error; this command is for debugging purpose. The 4 least significant bits form the error code. Bit 4 (Error Occurred) can be cleared by each new transfer. The power-on value is given in Table 39. This command is only useful during debugging. Table 40 gives an overview of the Error Codes.
Table 33 Power-on value for Set address FUNCTION Device address(1) Enable(2) Notes 1. The value written becomes the address. 2. A logic 1 enables the function. After a bus reset, the address is reset to 000 0000. The enable bit is set. The device will respond on packets for function address 000 0000, end-point 0 (default end-point). 2003 Jul 04 38 7 - 0 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 0 0 -
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
Table 34 Power-on value for Set end-points enable FUNCTION Enable all end-points Reserved 7 - - 6 - - 5 - - 4 - - 3 - -
TDA8030; TDA8031
2 - -
1 - -
0 0 -
Table 35 Power-on value for Read interrupt register FUNCTION Physical EP0 (control output end-point) Physical EP1 (control input end-point) Physical EP2 (generic output end-point) Physical EP3 (generic input end-point) Physical EP4 (generic input end-point) Physical EP5 (generic input end-point) Reserved Device Note 1. The Device event bit is cleared by issuing the Get Device Status command. Table 36 Read current frame number BYTE Byte 0 Byte 1 7 F 0 6 F 0 5 F 0 4 F 0 3 F 0 2 F F 1 F F 0 F F event(1) 7 - - - - - - - 0 6 - - - - - - 0 - 5 - - - - - 0 - - 4 - - - - 0 - - - 3 - - - 0 - - - - 2 - - 0 - - - - - 1 - 0 - - - - - - 0 0 - - - - - - -
Table 37 Set device status command functions FUNCTION Reserved Suspend - read/write TYPE INTERRUPT - no yes yes - 7 - - - - - 6 - - - - - 5 - - - - - 4 - - - 0 - 3 - - 0 - - 2 - 0 - - - 1 0 - - - - 0 0 - - - -
Suspend change read only; cleared on read Bus reset Reserved read only; cleared on read -
2003 Jul 04
39
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
Table 38 Set device status command function bits FUNCTION Suspend DESCRIPTION
TDA8030; TDA8031
The Suspend bit represents the current Suspend state. It is logic 1 when the device has not seen any activity on its upstream port for more than 3 ms. It is reset to logic 0 on any activity. When the device is suspended, (Suspend bit = 1) and the microcontroller writes logic 0 into it, the device will generate a remote wake-up. When the device is not suspended, writing a logic 0 has no effect. Writing a logic 1 in this register has no an effect.
Suspend Change
The Suspend Change bit is set to logic 1 when the Suspend bit toggles. The Suspend bit can toggle because: * The device goes into the suspended state * The device receives resume signalling on its upstream port * The Suspend Change bit is reset after the register has been read.
Bus reset
The Bus reset bit is set when the device receives a bus reset. It is cleared when read. On a bus reset, the device will automatically go to the default state (unconfigured and responding to address 0).
Table 39 Power-on value for Get Error Code FUNCTION Error code Error occurred Reserved Table 40 Error codes ERROR CODE[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DESCRIPTION no error PID encoding error unknown PID unexpected packet error in token CRC error in data CRC time-out error babble error in end of packet sent NAK sent Stall buffer overrun error reserved bitstuff error error in sync wrong toggle bit in data PID; ignored data 7 - - - 6 - - - 5 - - - 4 - 0 - 3 0 - - 2 0 - - 1 0 - - 0 0 - -
2003 Jul 04
40
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
Table 41 End-point commands COMMAND Select end-point DESCRIPTION
TDA8030; TDA8031
The select end-point command initializes an internal pointer to the start of the selected buffer. Optionally, this command can be followed by a data read, which returns some additional information on the packet in the buffer. The command code of the select end-point is equal to the physical end-point number. The power-on value is given in Tables 42 and 43. These commands are identical to Select End-point commands, but with the following differences: * They clear the associated interrupt * In the event of a control output end-point; they clear the set-up and overwritten bits * The read one byte is mandatory.
Select End-point/ Clear Interrupt
Set end-point status The Set end-point status command sets status bits 7 to 5 and 0 of the end-point. The command code is equal to the sum of 40H and the physical end-point number. Not all bits can be set for all types of end-points. The power-on value is given in Tables 44 and 45. Read buffer The Read buffer command is followed by a number of data reads, which return the contents of the selected end-point data buffer. After each read, the internal buffer pointer is incremented. The buffer pointer is not reset to the beginning of the buffer by the Read buffer command. This means that reading a buffer can be interrupted by any other command (except for the Select end-point). The data buffer organization is given in Table 46. Write buffer The Write buffer command is followed by a number of data writes, which load the data buffer of the selected end-point. After each write, the internal buffer pointer is incremented The buffer pointer is not reset to the beginning of the buffer by the Write buffer command. This means that writing to a buffer can be interrupted by any other command (except for the Select end-point and Select end-point/Clear Interrupt). The data buffer organization is given in Table 47. Clear buffer When a packet sent by the host has been received successfully, an internal end-point buffer full flag is set. All subsequent packets will be refused by returning a NAK. When the microcontroller has read the data, it should free the buffer by the Clear buffer command. When the buffer is cleared, new packets will be accepted. When bit 0 of the optional data byte is set to logic 1, the previously received packet was overwritten by a set-up packet. A buffer cannot be cleared when its Packet overwritten bit is set. The power-on value is given in Table 48. Validate buffer When the microcontroller has written data into an input buffer, it should set the buffer full flag by the Validate buffer command. This indicates that the data in the buffer is valid and can be sent to the host when the next input token is received. A control input buffer cannot be validated when the Packet overwritten bit of its corresponding output buffer is set.
2003 Jul 04
41
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
Table 42 Power-on value for Select end-point FUNCTION Full or empty Stall Set-up Packet overwritten Sent NAK Reserved 7 - - - - - - 6 - - - - - - 5 - - - - - - 4 - - - - 0 - 3 - - - 0 - -
TDA8030; TDA8031
2 - - 0 - - -
1 - 0 - - - -
0 0 - - - - -
Table 43 Description of the Power-on value for Select end-point bits FUNCTION Full or empty DESCRIPTION If set to logic 1, the buffer of the selected end-point is full. In the event of an output end-point, this bit is cleared by executing the Clear Buffer command, if the buffer was not overwritten. In the event of an input end-point, this bit is set by the Validate Buffer command. Stall Set-up If set to logic 1, the selected end-point is stalled. If set to logic 1, the last received packet for the selected end-point was a set-up packet. The value of this bit is updated after each successfully received packet (i.e. an ACKED package on that particular end-point). If set to logic 1, the previously received packet was overwritten by a set-up packet. The value of this bit is cleared by the Select End-point command. If set to logic 1, the device has sent a NAK. If the host sends an output packet to a filled output buffer, the device returns a NAK. If the host sends an input token to an empty input buffer, the device returns a NAK. This bit is set when a NAK is sent and the Interrupt On Nak feature is enabled. This bit is reset after the device has sent an ACK after an output packet or when the device has seen an ACK after sending an input packet. It is only defined for the 2 physical control end-points. Table 44 Power-on value for Set end-point status; notes 1 and 2 FUNCTION Stall Disable Rate feedback mode Interrupt unmasked Conditional stall Notes 1. X = dont care. 2. def means that the bit can be set if the end-point is of the specified type. 7 - - - 0 0 6 - - 0 - - 5 - 0 - - - 4 - - - - - 3 - - - - - 2 - - - - - 1 - - - - - 0 0 - - - - CTRL EP def X X X def GEN IN/OUT def def def X X GEN IN def def def X X
Packet overwritten Sent NAK
2003 Jul 04
42
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
Table 45 Description of the Power-on value for Set end-point status bits FUNCTION Stall Disable Rate feedback mode Interrupt unmasked Conditional stall If set to logic 1, the end-point is stalled. DESCRIPTION
TDA8030; TDA8031
If set to logic 1, the end-point is disabled. After a bus reset; each end-point is enabled, i.e. this bit is set to logic 0. If set to logic 0, the interrupt end-point is in toggle mode. If set to logic 1, the interrupt end-point is in rate feedback mode. If set to logic 1, an event on the end-point causes an interrupt to the microcontroller. If set to logic 1, both end-points zero are stalled; unless the set-up packet bit is set. A stalled control end-point is automatically unstalled when it receives a SET-UP token, regardless of the content of the packet. If the end-point stays in the stalled state, the microcontroller should re-install it. When a stalled end-point is unstalled (either by the Set end-point status command or by receiving a Set-up token) it is also re-initialized. This flushes the buffer: in case of an output buffer, it waits for a DATA 0 PID; in case of an input buffer, it writes a DATA 0 PID. Even when unstalled, setting the stalled bit to logic 0 initializes the end-point. When an end-point is stalled by the Set end-point status command, it is also re-initialized.
Table 46 Data buffer organization (read) BYTE Byte 0 Byte 1 Byte 2 .... Byte n + 1 Notes 1. Bit 7 of Byte 0 indicates whether the packet in the buffer was received successfully over the USB-bus. When this bit is set to logic 1, the packet was received successfully. 2. Bit 6 of Byte 0 indicates whether the packet in the buffer is a set-up packet. Table 47 Data buffer organization (write) BYTE Byte 0 Byte 1 Byte 2 .... Byte n + 1 Table 48 Power-on value for Clear buffer FUNCTION Packet overwritten Reserved 7 - - 6 - - 5 - - 4 - - 3 - - 2 - - 1 - - 0 0 - data byte n - 1 7 - - 6 - 5 - 4 - 3 - 2 - 1 - 0 0 data byte n - 1 7(1) 0/1 - 6(2) 0/1 5 - 4 - 3 - 2 - 1 - 0 0
number of data bytes in buffer data byte 0
number of data bytes in buffer data byte 0
2003 Jul 04
43
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
8.5.8 ANALOG INTERFACE 8.5.9 SUSPEND MODE
TDA8030; TDA8031
The transceiver interfaces directly to the USB cables through termination resistors. They are able to transmit and receive serial data at full speed (12 Mbits/s). A 1.5 k pull-up resistor is integrated between pins D+ and VDDD and is connected by software by the microcontroller; in case a 5% resistor is preferred, it can be externally connected between pins DELATT and D+ (DELATT is also controlled by software and is floating when OFF, or connected to VDDD when ON).
When the USB interface enters Suspend mode, the software should set the microcontroller in power-down mode in order to respect the suspend current condition. The following sequence should be executed: 1. When the device enters the Suspend mode, it generates an interrupt on pin INT1 2. The software should set USB_INT_MASK to logic 1 3. Then it should wait until CLK_EN_N is HIGH before entering power-down mode. When the device detects an activity on the bus, it resets CLK_EN_N to logic 0 and generates an interrupt on pin INT1. When leaving the Suspend mode, the following sequence should be executed: 1. The software should read the DEVICE_STATUS to enable the interrupt to be cleared 2. Reset USB_INT_MASK to logic 0.
2003 Jul 04
44
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDDU Vn Ptot Tstg Tj Vesd PARAMETER bus supply voltage input voltage on all pins total power dissipation IC storage temperature junction temperature electrostatic discharge voltage pins I/O, VCC, RST, C4, C8, CLK and PRES all other pins MM JEDEC MM JEDEC Vesd electrostatic discharge voltage pins I/O, VCC, RST, C4, C8, CLK and PRES all other pins Ilu latch-up free current on all pins TDA8031; HBM JEDEC TDA8030; HBM JEDEC CONDITIONS
TDA8030; TDA8031
MIN. -0.5 -0.5 - -55 - -5 -1 -50 -100 -6 -1.5
MAX. +6.5 +6.5 tbf +150 125 +5 +1 +50 +100 +6 +1.5 +100 V V
UNIT
mW C C kV kV V V kV kV mA
JEDEC; maximum -100 voltage is 1.5/-0.5 supply voltage of the block
10 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 63 UNIT K/W
2003 Jul 04
45
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
11 CHARACTERISTICS VDDU = 5 V; Tamb = 25 C; unless otherwise specified. SYMBOL Supplies VDDU VDD IDDU Isus supply voltage for the bus supply voltage after inrush current suppression switch supply current for the bus suspend current 5 V card; ICC = 40 mA; fclk = 6 MHz card inactive; microcontroller in power-down mode falling 4.2 4.2 - - PARAMETER CONDITIONS MIN.
TDA8030; TDA8031
TYP. - - - -
MAX.
UNIT
5.5 5.5 100 500
V V mA A
Vth(VDD) Vhys Vth(CDELAY) VCDELAY Io(CDELAY)
threshold voltage on VDD hysteresis voltage on Vth(VDD) threshold voltage on pin CDELAY voltage on pin CDELAY output current on pin CDELAY
3.6 150 - -
- - 1.25 - -2 9 22
3.8 350 - VDD + 0.3 - - - - +0.3VDDD VDDD + 0.3
V mV V V A mA nF
pin ground; charge current VCDELAY = VDD; discharge current
- - - - -0.3 0.7VDDD
CCDELAY fXTAL VIL VIH
capacitor on pin CDELAY
Crystal oscillator (XTAL1 and XTAL2) crystal frequency LOW-level input voltage on pin XTAL1 HIGH-level input voltage on pin XTAL1 12 - - MHz V V
DC-to-DC converter fclk VUP PE clock frequency output voltage power efficiency VCC = 5 V VCC = 3 or 1.8 V L = 6.8 H; C = 1 F VDDD voltage regulator VDDD output voltage PROG = 0 PROG = 1 (TDA8030 only) IDDD Cdec output current decoupling capacitor 3 4.5 0 1000 - - - - 3.6 5.5 25 - V V mA nF - - - - 12 5.5 5 85 - - - - MHz V V %
2003 Jul 04
46
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. - - - - - - - - -
MAX.
UNIT
Reset output to the card (RST) Vinact Iinact VOL VOH tr tf output voltage in inactive mode current from RST when inactive and pin grounded LOW-level output voltage HIGH-level output voltage rise time fall time IOL = 200 A IOL = 20 mA IOH = -200 A IOH = -20 mA CL = 100 pF; VCC = 5 or 3 V CL = 100 pF; VCC = 5 or 3 V no load Iinact = 1 mA no load Iinact = 1 mA 0 0 0 0 VCC - 0.4 0.9VCC 0 - - 0.1 0.3 -1 0.3 VCC VCC 0.4 0.1 0.1 V V mA V V V V s s
Clock output to the card (CLK) Vinact Iinact VOL VOH tr tf fclk output voltage in inactive mode current from CLK when inactive and pin grounded LOW-level output voltage HIGH-level output voltage rise time fall time clock frequency IOL = 200 A IOL = 70 mA IOH = -200 A IOH = -70 mA CL = 35 pF CL = 35 pF 1 MHz Idle configuration operational SR duty factor (except for XTAL) CL = 35 pF slew rate (rise and fall) CL = 30 pF 0 0 0 0 VCC - 0.4 0.9VCC 0 - - 1 0 45 0.2 - - - - - - - - - - - - - 0.1 0.3 -1 0.3 VCC VCC 0.4 16 16 1.5 12 55 - V V mA V V V V ns ns MHz MHz % V/ns
Card supply voltage (VCC) (2 ceramic multilayer capacitors with low ESR of minimum 100 nF should be used in order to meet these specifications) Vinact Iinact output voltage inactive current from VCC when inactive and pin grounded no load Iinact = 1 mA 0 0 - - - - 0.1 0.3 -1 V V mA
2003 Jul 04
47
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
SYMBOL VCC
PARAMETER output voltage
CONDITIONS active mode; ICC < 55 mA; 5 V card active mode; ICC < 55 mA; 3 V card active mode; current pulses of 40 nAs with I < 200 mA; t < 400 ns; f < 20 MHz; 5 V card active mode; current pulses of 24 nAs with I < 200 mA; t < 400 ns; f < 20 MHz; 3 V card 4.75 2.78 4.6
MIN.
TYP. 5 3 -
MAX. 5.25 3.22 5.4
UNIT V V V
2.75
-
3.25
V
active mode; 1.64 ICC < 35 mA; 1.8 V card active mode; current pulses of 12 nAs with I < 200 mA; t < 400 ns; f < 20 MHz; 1.8 V card ICC output current 5 V card; from 0 to 5 V 3 V card; from 0 to 3 V 1.8 V card; from 0 to 1.8 V when clock is stopped; at all VCC values VCC shorted to ground SR Vripple(p-p) slew rate ripple voltage on VCC (peak-to-peak value) up or down (maximum capacitance = 300 nF) 20 kHz < f < 200 MHz 5 V card 3 V card 1.8 V card Data line (I/O); I/O has an integrated 14 k pull-up resistor at VCC Vinact Iinact VOL output voltage inactive current from I/O when inactive and pin grounded LOW-level output voltage the I/O is configured as an output IOL = 1 mA IOL = 10 mA 0 VCC - 0.4 no load Iinact = 1 mA 0 - - - - - 1.62
1.8 -
1.96 1.98
V V
- - - - - 0.05
- - - - - 0.16
-55 -55 -35 -10 -120 0.22
mA mA mA mA mA V/s
- - - - - -
350 200 100
mV mV mV
0.1 0.3 -1
V V mA
- -
0.3 VCC
V V
2003 Jul 04
48
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
SYMBOL VOH
PARAMETER HIGH-level output voltage
CONDITIONS the I/O is configured as an output IOH < -20 A IOH < -40 A; 5 and 3 V card IOH = -10 mA
MIN.
TYP.
MAX.
UNIT
0.8VCC 0.75VCC 0 -0.3 1.5 - - - - 11
-
VCC + 0.25 VCC + 0.25
V V V V V A A s s k ns
- - - - - - - 14 -
0.4 +0.8 VCC 500 10 1.2 0.1 17 3/fXTAL1
VIL VIH IIL ILIH ti(tr) to(tr) Rpu tW(pu)
LOW-level input voltage HIGH-level input voltage LOW-level input current on I/O HIGH-level input leakage current on I/O input transition times output transition times internal pull-up resistance between I/O and VCC width of active pull-up pulse
the I/O is configured as an input the I/O is configured as an input VIL = 0 VIH = VCC CL 60 pF; 5 or 3 V card CL 60 pF 5 or 3 V card
the I/O is configured as an 2/fXTAL1 output; LOW-to-HIGH transition VOH = 0.9VCC; CL = 60 pF
2/fXTAL1
Ipu
current from I/O when active pull-up pulse
-1
-
-
mA
Auxiliary contacts C4/C8; integrated 10 k pull-up resistor to VCC Vinact Iinact VOL output voltage inactive current from I/O when inactive and pin grounded LOW-level output voltage C4 and C8 configured as an output; IOL = 1 mA C4 and C8 configured as an output; IOH < -40 A; 5 and 3 V card C4 and C8 configured as an input C4 and C8 configured as an input VIL = 0 VIH = VCC no load Iinact = 1 mA 0 - - 0 - - - - 0.1 0.3 -1 0.3 V V mA V
VOH
HIGH-level output voltage
0.8VCC
-
VCC + 0.25
V
VIL VIH IIL ILIH
LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input leakage current
-0.3 1.5 - -
- - - -
+0.8 VCC 500 10
V V A A
2003 Jul 04
49
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
SYMBOL ti(tr) to(tr) Rpu tW(pu)
PARAMETER input transition times output transition times internal pull-up resistance between C4/C8 and VCC width of active pull-up pulse
CONDITIONS CL 60 pF CL 60 pF - - 8 the I/O is configured as an output; LOW-to-HIGH transition VOH = 0.9VCC; CL = 60 pF -
MIN.
TYP. - - 10 200 1.2 0.1 12 -
MAX.
UNIT s s k ns
Ipu Timing tact tde
current from C4 and C8 when active pull-up
-1
-
-
mA
activation sequence duration deactivation sequence duration
- -
- -
160 100
s s
Protections and limitations ICC(sd) II/O(lim) ICLK(lim) IRST(lim) IRST(sd) Tsd VIL VIH IIL IIH VIL VIH VOL VOH IIL ITL shutdown and limitation current at VCC limitation current on I/O limitation current on pin CLK limitation current on pin RST shutdown current on pin RST shutdown temperature - -10 -70 -20 - - - 0.7VDDD VIN = 0 VIN = VDD - - - 0.2VDDD + 0.9 IOL = 1.6 mA IOH = -30 A VI = 0.4 V VI = 2 V - VDDD - 0.7 -1 - -100 - - - -20 150 - - - - - - - - - - - +10 +70 +20 - - 0.3VDDD - 20 20 0.2VDDD - 0.4 - -50 -650 mA mA mA mA mA C V V A A V V V V A A
Card presence input; pin PRES LOW-level input voltage HIGH-level input voltage input leakage current low input leakage current high
General purpose I/Os; pins P0X, P1X, P2X and P3X LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage LOW-level input current HIGH-to-LOW transition current
Pins ALE and PSEN VOL VOH LOW-level output voltage HIGH-level output voltage IOL = 3.2 mA IOH = -3.2 mA - VDDD - 0.7 - - 0.4 - V V
2003 Jul 04
50
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
SYMBOL Pin EA/VPP VIL VIH Vprog VIL VIH VOH IL VIL VIH
PARAMETER
CONDITIONS -
MIN.
TYP. - - 12.75 - - - - - -
MAX.
UNIT
LOW-level input voltage HIGH-level input voltage programming voltage TDA8030
0.2VDDD - 13
V V V
0.2VDDD + 0.9 12.5 - 0.7VDDD when switched on; IOH = 2 mA when switched off 3.0 - - 0.7VDD
Reset input; pin RESET (active HIGH) LOW-level input voltage HIGH-level input voltage 0.2VDDD - 3.6 10 V V
DELATT output pin; optional connection for an external 1.5 k resistor on pin D+ HIGH-level output voltage leakage current V A V V
Programming input; pin PROG (active HIGH) and Test input; pin TEST (active HIGH) LOW-level input voltage HIGH-level input voltage 0.2VDD -
ATX Transceiver DRIVER CHARACTERISTICS IN FULL-SPEED MODE; PINS D+ AND D- VOL(stat) VOH(stat) Ro(drive) ttr tRFM Vcross Rint(DP) LOW-level static output voltage HIGH-level static output voltage driver output resistance transition times rise and fall time matching output signal crossover voltage integrated resistor on DP when connected USB_SOFTCONNECT active excluding outside resistors CL = 50 pF CL = 50 pF RL = 1.5 k - 2.8 10 4 90 1.3 1.1 - - - - - - - 0.3 3.6 30 20 110 2 1.9 V V ns % V k
RECEIVER CHARACTERISTICS IN FULL-SPEED MODE; PINS ATXDP AND ATXDM Vi(dif) Vdif(CM) Vth(SE) differential input sensitivity differential common mode range in which Vi(dif) applies single-ended receiver threshold 0.2 0.8 0.8 - - - - 2.5 2.0 V V V
2003 Jul 04
51
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
andbook, full pagewidth
DELATT
CPROG
PRES
J2
C5I C6I C7I C8I C1I C2I C3I C4I K1 K2
RESET
RFU
RFU
RFU
RFU
P17
P16
P15
P14
P13
16 15 14 13 12 11 10 9 C4 17 CGND 18 CLK 19 VCC 20 RST 21 TEST 22 VUP 23 LX 24 STGND 25 VDD 26 VDDU 27 UGND 28 D+ 29 D- 30 CDELAY 31 P30/RxD 32 P32/INT0 P33/INT1 P36/WR P34 P35 P31/TXD P37/RD C7 22 nF R4 0 R3 0
1
8
7
6
5
4
3
2
P12
I/O
C8
XTAL1 VDDD
XTAL2
GNDD
P20/A8
P21/A9
P22/A10
P23/A11
J1 1 6 GND 4
PDATA VCC NDATA 2
P24/A12
2003 Jul 04
R1 0 C1 100 nF C2 100 nF CARD_READ_CCM0_2251 VDDD TP18 GND
12 APPLICATION INFORMATION
Philips Semiconductors
USB smart card reader (OTP or ROM)
VDDD
1 3
MICROCOSMOS BP1
2 4
1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P11 P10 P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 EA/VPP ALE/PROG PSEN P27/A15 P26/A14 P25/A13 VDDD
IC1
TDA8030
52
VDDU
D1 BAT54
VDD L1 6.8 H
C3 1 F
C5 10 F (10 V)
C6 100 nF R2 1.5 k
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
TDA8030; TDA8031
5 3
1
C12 22 pF C13 22 pF
2
2
Y1 12 MHz
C8 1 F VDDD
MGU892
Product specification
Fig.12 Application diagram. (More details in application note AN01013).
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
13 PACKAGE OUTLINE LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
TDA8030; TDA8031
SOT314-2
c
y X A 48 49 33 32 ZE
e E HE wM bp 64 1 pin 1 index 16 ZD bp D HD wM B vM B vM A 17 detail X L Lp A A2 A1 (A 3)
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7 0o
o
12.15 12.15 11.85 11.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT314-2 REFERENCES IEC 136E10 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
2003 Jul 04
53
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
14 SOLDERING 14.1 Introduction to soldering surface mount packages
TDA8030; TDA8031
To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 14.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 220 C (SnPb process) or below 245 C (Pb-free process) - for all BGA and SSOP-T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 235 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 14.3 Wave soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.
2003 Jul 04
54
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
14.5
TDA8030; TDA8031
Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable
BGA, LBGA, LFBGA, SQFP, SSOP-T(3), TFBGA, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(5), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP Notes
not suitable not suitable(4)
suitable not not recommended(5)(6) recommended(7)
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2003 Jul 04
55
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
15 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development
TDA8030; TDA8031
DEFINITION This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 17 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2003 Jul 04
56
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613502/01/pp57
Date of release: 2003
Jul 04
Document order number:
9397 750 10125

▲Up To Search▲

Price & Availability of TDA8030

	To Download TDA8030 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .